Nabihah@nornabihah Ahmad

Citation

Thesis Title
Novel Digital VLSI Implementation of Data Encryption Algorithm using Nano-Metric CMOS Technology

Read article at Massey Research Online:

Mrs Nabihah proposed a new 8-bit stream cipher architecture core for an application specific integrated circuit AES crypto-processor. Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require a low power consumption and low cost design. The chip area and power are optimised along with high throughput by employing circuit-level techniques, resource sharing and low supply voltage. She proposed design includes a novel S-box/ InvS-box, MixColumn/ InvMixColumn and ShiftRow/ InvShiftRow with a novel low power Exclusive OR (XOR) gate applied to all sub systems to minimise the power consumption. This thesis also describes a new fault detection scheme for S-box/ InvS-box that is parity prediction based to protect the key from fault attacks.

Supervisors
Professor Rezaul Hasan
Dr Tom Moir